Example embodiments relate to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus using a protocol between an NAND flash memory device and a controller, which may efficiently correct a plurality of error bits existing in a single section while reducing bus traffic in a multi-level cell flash memory device supporting internal copy-back.
As flash memory devices have increased in capacity, a flash memory device may include a plurality of chips CIP1 through CIPn connected to a single bus BUS, as illustrated in FIG. 1. The chips CIP1 through CIPn may share a controller CTRL connected to the bus BUS. In order to reduce bus traffic, such a multi-chip type flash memory device may support internal copy-back.
Internal copy-back is a protocol in which an external input/output (I/O) bus may not be required since a page buffer P_BUF inside a chip may be used when a page PAGEi is copied on another page PAGEj, as illustrated in FIG. 2.
However, the conventional flash memory device may detect and correct an error by using an error correcting circuit, which may be included in a controller CTRL as is illustrated in FIG. 1, included outside of a chip. A conventional method of detecting and correcting an error will be described in detail.
FIG. 3 is a block diagram of a conventional semiconductor chip 100 having an error correcting circuit and a flash memory device.
Referring to FIG. 3, the semiconductor chip 100 may include a flash memory cell array 120 and an error correcting circuit 140. The semiconductor chip 100 may be connected to an external circuit (not shown) via a bus 200. The error correcting circuit 140 may include a NAND interface 141, an error correction encoding circuit 142, and an error correction decoding circuit 143.
The error correction encoding circuit 142 may receive normal data NDTA that is to be stored in the flash memory cell array 120, and may generate corresponding parity data PDTA. The normal data NDTA and the parity data PDTA may be respectively stored in a normal data region (not shown) and a parity data region (not shown) of the flash memory cell array 120.
The error correction decoding circuit 143 may detect and correct an error in the normal data NDTA when reading the normal data NDTA from the memory cell array 120.
In this case, error correction may be performed using the BCH (Bose-Chaudhuri-Hocquenghem) error correction algorithm. The BCH error correction algorithm may be capable of correcting multiple bits of error in a data block, and thus has been widely applied to error correction in communication systems and memory systems.
In particular, in the case of a multi-level cell flash memory device that stores multiple bits in a cell, bit errors may be very likely to occur. Thus, error correction is preferably performed using the BCH error correction algorithm capable of correcting multiple bits of error.
Error correction using the BCH algorithm, and particularly, error correction using binary BCH 4148, 4096 code data (hereinafter referred to as “BCH code data”) will be described in detail. However, example embodiments are not limited to the size of binary BCH code data that will be described.
In general, in error correction using the BCH algorithm, BCH code data may be generated using an error correcting encoder, and decoded using an error correcting decoder. Specifically, the BCH code data may be decoded by calculating syndromes, constructing an error locator polynomial using the syndromes, and calculating the locations of error bits by obtaining the root of the error locator polynomial. In particular, in order to decode binary BCH code data, an error may be corrected by inverting the bit value of an error bit.
FIG. 4 is a conceptual diagram illustrating the format of BCH code data CDATA.
Referring to FIG. 4, the BCH code data CDTA may consist of 512-byte normal data NDTA and 7-byte parity data PDTA. The parity data PDTA may consist of 48-bit parity data and 4-bit dummy data.
FIG. 5 is a diagram illustrating the format of a plurality of pieces of normal data NDTA and a plurality of pieces of parity data PDTA that are stored within one page of a NAND flash memory device.
In particular, FIG. 5 illustrates a page PAGEn with a 2K byte normal data region NStorage and 64 byte parity data region PStorage. Accordingly, four pieces of 512-byte normal data NDTA1 through NDTA4 and four pieces of parity data P1 through P4 that may respectively correspond to the normal data NDTA1 through NDTA4, are stored in the page PAGEn.
Likewise, since the conventional flash memory device may need to transmit and receive normal data and parity data to and from the memory cell array and the error correcting circuit via a bus in order to detect and correct an error, bus traffic might occur. Thus, internal copy-back in the conventional flash memory device may not be efficient.